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HT46R63/HT46C63 A/D with LCD Type 8-Bit MCU
Features
* Operating voltage: * 8-level stack * Up to 0.5ms instruction cycle with 8MHz system clock
fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V
* Operating frequency: External RC or Crystal * 32.768kHz crystal oscillator used for timing purposes * Watchdog enable or disable function * 1x16 bits timer with an overflow interrupt (TMR) * Time base generator (clock source: 32.768kHz)
at VDD=5V
* 2 external interrupts (high/low going trigger) * One comparator * LCD: 203 or 194, 1/3 bias with 12 pins logical
outputs options. (select by options in unit of 4 pins, 8 high sink)
* Built-in R type bias generator * 8 channels 8-bits resolution A/D converter * 4 channels PWM outputs * 56-pin SSOP, 100-pin QFP package
and RTC interrupts
* 4K15 program memory * 2088 data memory RAM * Maximum of 32 I/O lines (shared with INT0, INT1,
TMR, AN0~AN7, PWM0~PWM3)
General Description
The HT46R63/HT46C63 are 8-bit, high performance, RISC architecture microcontroller devices specifically designed for A/D product applications that interface directly to analog signals and which require LCD Interface. The mask version HT46C63 is fully pin and functionally compatible with the OTP version HT46R63 device. The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, multi-channel A/D Converter, Pulse Width Modulation function, HALT and wake-up functions, in addition to a flexible and configurable LCD interface enhance the versatility of these devices to control a wide range of applications requiring analog signal processing and LCD interfacing, such as electronic metering, environmental monitoring, handheld measurement tools, motor driving, etc., for both industrial and home appliance application areas.
Rev. 1.90
1
May 17, 2004
HT46R63/HT46C63
Block Diagram
IN T 0 /IN T 1
TM RC TM R
M U
fS X
YS
/4
TM R
In te rru p t C ir c u it 4k15 P ro g ra m ROM P ro g ra m C o u n te r S ta c k 8 L e v e ls IN T C 0 IN T C 1 W DT G e n e ra to r
E N /D IS WDT M U X RTCOSC W DTOSC fS Y S /4
T im e B a s e /R T C /L C D In s tr u c tio n R e g is te r RE VD VS AVD D In s tr u c tio n D ecoder ALU OSC3 OSC4 T im in g G e n e ra to r S h ifte r MUX S D S PB PBC 8 -C h a n n e l A /D STATUS PC PCC PORT C PORT B
G e n e ra to r
MP
M U
X
DATA RAM (2 0 8 8 )
PA PAC
PORT A
PA0~PA7
P B 0 /A N 0 ~ P B 7 /A N 7 C o n v e rte r
PC 0~PC7
OSC2
OSC1
ACC
LVR
O p tio n PROM
PD PDC PW M PORT D
H ig h M id d le Low
R -B IA S
LC D 4 1 9 /3 2 0 L o g ic a l O u tp u t O p tio n
PD PD PD PD PD
0/ 4/ 5/ 6/ 7
P W M 0 ~ P D 3 /P W IN T 0 IN T 1 TM R
M3
C o m p a ra to r E N /D IS f
RTC
C H G O ,C M PO C M PP,C M PN
VLCD
C O M 0 ~ C O M 3 /S E G 1 9 SEG 0~SEG 18
HALT
Rev. 1.90
2
May 17, 2004
HT46R63/HT46C63
Pin Assignment
VL CM CM CM CH OS OS V OS OS R NC NC CD PN PP PO GO C4 C3 DD C2 C1 ES NC NC NC NC NC NC NC
OSC4 OSC3 VDD OSC2 OSC1 RES PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 VSS P B 0 /A N 0 P B 1 /A N 1 P B 2 /A N 2 P B 3 /A N 3 AVDD PC0 PC1 PC2 PC3 P D 0 /P W M 0 P D 1 /P W M 1 P D 2 /P W M 2 P D 3 /P W M 3 9 8 7 6 5 4 3 2
1
56 55 54 53 52 51 50 49 48 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
CHGO CMPO CMPP CMPN VLCD COM0 COM1 COM2 C O M 3 /S E G 1 9 SEG 14 SEG 13 SEG 12 SEG 11 SEG 10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 PD7 P D 6 /T M R P D 5 /IN T 1 PB PB PB PB PB PB PB PB 0 1 2 3 4 5 6 7 A NC NC N PA PA PA PA PA PA PA PA VS /A N /A N /A N /A N /A N /A N /A N /A N VD N N N N N N N N NC C 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
100 1
81
80
NC NC NC NC NC NC COM COM COM COM SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG NC 0 2 3 /S E G 1 9 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1
S
H T 4 6 R 6 3 /H T 4 6 C 6 3 1 0 0 Q F P -A
D C C C C C C C C
30
31
50
51
PD PD PD PD PD PD PD PD PC PC PC PC PC PC PC PC
NC
NC
NC
NC
P D 4 /IN T 0
7 6 /T 5 /IN 4 /IN 3 /P 2 /P 1 /P 0 /P
7 6 5 4 3 2 1 0
H T 4 6 R 6 3 /H T 4 6 C 6 3 5 6 S S O P -A
MR T1 T0 WM3 WM2 WM1 WM0
Rev. 1.90
3
May 17, 2004
HT46R63/HT46C63
Pad Assignment
HT46C63
CHGO CMPO CMPN CMPP COM0 OSC3 OSC4 OSC1 OSC2 VLCD VDD RES 72 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 VSS VSS A N 0 /P B 0 A N 1 /P B 1 A N 2 /P B 2 A N 3 /P B 3 A N 4 /P B 4 A N 5 /P B 5 A N 6 /P B 6 A N 7 /P B 7
69 71 70
68
67
66 64
65 62
63 60
61
59
58
57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38
COM1 COM2 C O M 3 /S E G 1 9 SEG 18 SEG 17 SEG 16 SEG 15 SEG 14 SEG 13 SEG 12 SEG 11 SEG 10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1
T R IM 3
T R IM 2
T R IM 1
(0 , 0 )
19
20 PC0
21 PC1
22 PC2
23 PC3
24 PC4
25 PC5
26 PC6
27 PC7
28 P D 0 /P W M 0
29 P D 1 /P W M 1
30 P D 2 /P W M 2
31 P D 3 /P W M 3
32 P D 4 /IN T 0
33 P D 5 /IN T 1
34 P D 6 /T M R
35 PD7
36
37
SEG0
* The IC substrate should be connected to VSS in the PCB layout artwork.
AVDD
Pin Description
Pin Name PA0~PA7 I/O I/O Option Pull-high Wake-up Description I/O lines with pull-high resistors (bit option). I/O modes of each line are controlled by related control register bit (PAC). Each line of PA can be optioned as a wake-up input (bit option). I/O configurations: Schmitt trigger/CMOS I/O lines with pull-high resistors (bit option). I/O modes of each line are controlled by related control register bit (PBC). I/O configurations: Schmitt trigger/CMOS. Each PB line is pin shared with an A/D converter input. I/O lines with pull-high resistors (bit option). I/O modes of each line are controlled by related control register bit (PCC). I/O configurations: Schmitt trigger/CMOS.
PB0/AN0~ PB7/AN7 PC0~PC6, PC7 PD0/PWM0~ PD3/PWM3, PD4/INT0, PD5/INT1, PD6/TMR, PD7
I/O
Pull-High
I/O
Pull-High
I/O
I/O lines with pull-high resistors (bit option). I/O modes of each line are conPull-High PWM trolled by related control register bit (PDC). I/O configurations: Schmitt trigInterrupt Falling ger/CMOS. The PD0~PD3 can be selected as PWM outputs. INT0/INT1 and/or Rising are falling/rising edge selectable triggers.
Rev. 1.90
4
May 17, 2004
HT46R63/HT46C63
Pin Name OSC1 OSC2 OSC3 OSC4 CMPN CMPP CMPO CHGO VDD AVDD VSS RES VLCD SEG0~SEG18 COM0~COM2 COM3/SEG19 I/O I O I O I I O O 3/4 3/4 3/4 I I/O O Option RC or crystal 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 SEG7~SEG18 logical CMOS COM3 or SEG19 Description A resistor across OSC1 and VDD or a crystal across OSC1 and OSC2 will generate a system clock. 32768Hz crystal across OSC3 and OSC4 will generate RTC clock signal which only provides system timing. Negative input for comparator Positive input for comparator Comparator output Comparator output with 32768Hz carrier Positive power supply A/D converter Positive power supply, AVDD should be externally connected to VDD Negative power supply, ground Schmitt trigger reset input LCD highest voltage; should be connected to VDD with external resistor. LCD segment signal driving outputs SEG7~SEG10 can be optioned as output lines. SEG11~SEG14, SEG15~SEG18 can be optioned as a high sinking output lines. LCD common signal driving outputs
O
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Test Conditions Symbol Parameter VDD VDD Operating Voltage Operating Current (RC OSC) (Analog Circuit Disabled) Operating Current (RC OSC) Operating Current Standby Current (WDT OSC On, RTC Off, LCD Off) Standby Current (WDT OSC Off, RTC Off, LCD Off) 3/4 3V 5V 3V 5V 5V No load, fSYS=8MHz 3V No load, 5V System HALT 3V System HALT 5V No load, fSYS=4MHz Conditions fSYS=4MHz fSYS=8MHz No load, fSYS=4MHz 2.2 3.3 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 1 3 1 3 3 3/4 3/4 3/4 3/4 5.5 5.5 2 Min. Typ. Max.
Ta=25C Unit V V mA 5 2 mA 5 5 5 15 1 1 mA mA
IDD1
IDD2 IDD3 ISTB1
ISTB2
mA
Rev. 1.90
5
May 17, 2004
HT46R63/HT46C63
Test Conditions Symbol Parameter VDD ISTB3 Standby Current (WDT OSC Off, RTC On, LCD Off) Standby Current (WDT OSC Off, RTC On, LCD On with Low Current Internal R Type Bias Option) Standby Current (WDT OSC Off, RTC On, LCD On with Middle Current Internal R Type Bias Option) 3V System HALT 5V System HALT 5V VLCD=VDD System HALT 5V VLCD=VDD 3V 3V Conditions 3/4 3/4 10 20 16 32 38 76 0 0.7VDD 0 0.9VDD 0 -2 -5 6 10 VOH=0.9VDD -2 -4 8 16 VOL=0.1VDD 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 16 32 3/4 3/4 20 10 -10 0.2 0 3/4 3/4 3/4 3/4 3/4 12 24 20 40 52 104 3/4 3/4 3/4 3/4 3/4 -4 -8 12 25 -4 -8 3/4 3/4 3/4 3/4 3/4 3/4 60 30 3/4 3/4 3/4 0.5 0.5 1.5 5 15 16 32 26 52 68 136 0.3VDD 3 0.4VDD VDD VDD 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 -100 100 100 50 10 VDD-0.8 VDD 1 1 3 kW mV V V LSB mA mA mA V V V V V mA mA mA mA Min. Typ. Max. Unit
ISTB4
ISTB5
ISTB6 VIL1 VIH1 VIL2 VIH2 VLCD IOH1
3V Standby Current (WDT OSC Off, System HALT RTC On, LCD On with High Current 5V VLCD=VDD Internal R Type Bias Option) Input Low Voltage for I/O Ports Input High Voltage for I/O Ports Input Low Voltage (RES) Input High Voltage (RES) LCD Highest Voltage I/O Port Source Current 5V 3V I/O Port Sink Current 5V 3V SEG7~18 Logical Source Current 5V 3V SEG7~10 Logical Sink Current 5V 3V SEG11~18 Logical Sink Current 5V I/O Port Total Source Current I/O Port Total Sink Current Pull-High Resistance (I/O) 5V Comparator Input Offset Voltage Comparator Input Voltage Range A/D Input Voltage 3/4 3/4 3/4 3/4 3/4 3V 3/4 3/4 3/4 3/4 3/4 3V 3/4 3/4 3/4 3/4 3/4 VOH=0.9VDD
IOL1
VOL=0.1VDD
mA
IOH2
mA
IOL2
VOL=0.1VDD
mA
IOL3 IOHTOTAL IOLTOTAL RPH VOS VI VAD EAD
mA mA mA
A/D Conversion Integral Nonlinearity 3/4 Error Additional Power Consumption if A/D Converter is Used 3V 5V
IADC
Rev. 1.90
6
May 17, 2004
HT46R63/HT46C63
A.C. Characteristics
Test Conditions Symbol Parameter VDD fSYS1 System Clock (Crystal) System Clock (32768Hz Crystal OSC) Timer Input Frequency 3/4 3/4 3/4 3/4 3/4 3V Watchdog Oscillator Period 5V Watchdog Time-out Period External Reset Low Pulse Width System Start-up Timer Period Interrupt Pulse Width A/D Clock Period A/D Conversion Time A/D Sampling Time Response Time of Comparator 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Conditions 2.2V~5.5V 3.3V~5.5V 2.2V~5.5V 2.2V~5.5V 3.3V~5.5V 3/4 400 400 3/4 0 0 45 32 3/4 3/4 32768 3/4 3/4 90 65 4000 kHz 8000 3/4 4000 kHz 8000 180 130 ms Hz Min. Typ. Max. Unit Ta=25C
fSYS2
fTIMER
tWDTOSC
tWDT tRES tSST tINT tAD tADC tADCS tCOMP
Note: tSYS=4/fSYS 3/4 Power-up or wake-up from HALT 3/4 3/4 3/4 3/4 3/4 1 3/4 1 1 64 3/4 3/4
65536 tSYS or 65536 tWDTOSC or 65536 tRTCOSC 3/4 1024 3/4 3/4 3/4 32 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3 ms tSYS ms ms tAD tAD ms
Note: tSYS=1/fSYS
Rev. 1.90
7
May 17, 2004
HT46R63/HT46C63
Functional Description
Execution Flow The system clock for the microcontroller is derived from an external RC or crystal oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of 4 system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch and decoding takes an instruction cycle while execution take the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The program counter controls the sequence in which the instructions stored in the program memory are executed and its contents specify full range of program memory. After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading PCL (program counter lower-order byte register), subroutine call, initial reset, interrupts or return from subroutine or interrupts, the program counter manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction. The lower-order byte of the program counter (PCL) can be accessed by using software instructions. Moving data into the PCL performs a short jump. The destination will be within the current program ROM page. Once the control transfer takes place, the execution suffers from having an additional dummy cycle. Program Memory - PROM The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into
T2 T3 T4 T1 T2 T3 T4
S y s te m
C lo c k PC
T1
T2
T3
T4
T1
PC
PC+1
PC+2
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution Flow Program Counter *11~*8 0000 0000 0000 0000 0000 0000 0000 @11~@8 #11~#8 S11~S8 *7 0 0 0 0 0 0 0 @7 #7 S7 *6 0 0 0 0 0 0 0 @6 #6 S6 *5 0 0 0 0 0 0 0 @5 #5 S5 *4 0 0 0 0 1 1 1 PC+2 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0 *3 0 0 1 1 0 0 1 *2 0 1 0 1 0 1 0 *1 0 0 0 0 0 0 0 *0 0 0 0 0 0 0 0
Mode Initial Reset External Interrupt 0 External Interrupt 1 Timer/Event Counter Overflow Time Base Time-out A/D Interrupt RTC Interrupt Skip Loading PCL Jump, Call Branch Return (RET, RETI)
Program Counter Note: *11~*0: Program counter bits #11~#0: Instruction code bits S11~S0: Stack register bits @7~@0: PCL bits
Rev. 1.90
8
May 17, 2004
HT46R63/HT46C63
409615 bits, addressed by the program counter and table pointer. Certain locations in the program memory are reserved for special usage:
* Location 000H
000H 004H E x te r n a l In te r r u p t 0 S u b r o u tin e 008H E x te r n a l In te r r u p t 1 S u b r o u tin e 00C H 010H 014H 018H RTC T im e - o u t In te r r u p t s u b r o u tin e T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e T im e B a s e T im e - o u t In te r r u p t S u b r o u tin e A /D C o n v e r te r E O C In te r r u p t S u b r o u tin e D e v ic e In itia liz a tio n P r o g r a m
This area is reserved for program initialization. After chip reset, the program always begins execution at location 000H.
* Location 004H
P ro g ra m M e m o ry
This area is reserved for the external interrupt 0 service program. If the INT0 input pin is activated, the interrupt is enabled and the stack is not full, the program begins execution at this location.
* Location 008H
n00H L o o k - u p T a b le ( 2 5 6 w o r d s ) nFFH F00H FFFH L o o k - u p T a b le ( 2 5 6 w o r d s ) 1 5 b its N o te : n ra n g e s fro m 0 to F
This area is reserved for the external interrupt 1 service program. If the INT1 input pin is activated, the interrupt is enabled and the stack is not full, the program begins execution at this location.
* Location 00CH
This area is reserved for the timer/event counter interrupt service program. If a timer interrupt results from a timer/event counter overflow, and the interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
* Location 010H
Program Memory higher-order byte to lower portion of TBLH(08H) and the remaining bits (1 bits) of TBLH are read as 0. The table pointer (TBLP) is read/write register (07H), which indicates the table location. Before accessing the table, the location has to be placed in TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR(interrupt service routine) both employ the table read instruction, the contents of TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors are thus brought about. Given this, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both main routine and the ISR, the interrupt is supposed to be disabled prior to the table read instruction. It will not be enabled until the TBLH in the main routine has been backup. All table related instructions require two cycles to complete the operation. These areas may function as normal program memory depending upon the requirements. Stack Register - STACK This is a special part of memory, which is used to save the contents of the program counter only. The stack is organized into 8 levels and is neither part of the data not programmable space, and is not accessible. The activated level is indexed by the stack pointer and is not acTable Location
This area is reserved for the time base interrupt service program. If the a time base time-out occurs, the interrupt is enabled and the stack is not full, the program begins execution at this location.
* Location 014H
This area is reserved for the A/D converter interrupt service program. If the interrupt is activated (when the A/D conversion is completed), the interrupt is enabled and the stack is not full, the program begins execution at this location.
* Location 018H
This area is reserved for the RTC interrupt service program. When the RTC time-out occurs, the interrupt is enabled and the stack is not full, the program begins execution at this location.
* Table location
Any location in the program memory can be used as look-up tables. The instructions TABRDC [m] (the current page, 1 page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the
Instruction *11 TABRDC [m] TABRDL [m] P11 1 *10 P10 1 *9 P9 1 *8 P8 1 *7 @7 @7 *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0
Table Location Note: *11~*0: Table location bits @7~@0: Table pointer bits Rev. 1.90 9 May 17, 2004 P11~P8: Current program counter bits
HT46R63/HT46C63
c e s s ib l e. A t a s ubr o u t i ne c a l l o r i n t e r r u p t acknowledgment, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After a chip reset, the stack pointer will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. When the stack pointer is decreased (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. In similar case, if the stack is full and a call is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent 8 return addresses are stored). Data Memory - RAM The data memory is designed with 2398 bits. The data memory is divided into two functional groups: special function registers and general purpose data memory (2088). Most are read/write, but some are read only. The special function registers include the indirect addressing register 0 and 1 (R0;00H, R1;02H), memory pointer 0 and 1 (MP0;01H, MP1;03H), bank pointer (BP:04H), accumulator (ACC;05H), program counter lower-order byte register (PCL;06H), table pointer (TBLP;07H), table higher-order byte register (TBLH;08H), real time clock control register (RTCC;09H), status register (STATUS;0AH), interrupt control register (INTC0;0BH), timer higher-order byte register (TMRH;0CH), timer lower-order byte register (TMRL;0DH), timer control register (TMRC;0EH), I/O port data registers (PA;12H, PB;14H, PC;16H, PD;18H), I/O port control registers (PAC;13H, PBC;15H, PCC;17H, PDC;19H), PWM0 (1AH), PWM1 (1BH), PWM2 (1CH), PWM3 (1DH), INTC1 (1EH),the A/D result register (ADR;21H), the A/D control register (ADCR;22H) and the A/D clock setting register (ACSR;23H). The remaining space before the 30H is reserved for future expansion and reading these locations will return the result 00H. The general-purpose data memory, addressed from 30H to FFH, is used for data and control information under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and cleared by SET [m].i and CLR [m].i, respectively. They are also indirectly accessible through memory pointers (MP0 and MP1).
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H ADR ADCR ACSR PA PAC PB PBC PC PCC PD PDC PW M0 PW M1 PW M2 PW M3 IN T C 1 S p e c ia l P u r p o s e DATA M EM ORY In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1 BP ACC PCL TBLP TBLH RTCC STATUS IN T C 0 TM RH TM RL TM RC
2FH 30H
FFH
G e n e ra l P u rp o s e D a ta M e m o ry (2 0 8 B y te s )
:U nused R e a d a s "0 0 "
RAM Mapping
Indirect Addressing Register Location 00H (02H) is indirect addressing registers that are not physically implemented. Any read/write operation of [00H] ([02H]) will access data memory pointed to by MP0 (MP1). Reading location 00H (02H) itself indirectly will return the result 00H. Writing indirectly results in no operation. The memory pointers are 8-bit registers. Only the MP1/R1 can be used to access the LCD RAM (BP=1).
Rev. 1.90
10
May 17, 2004
HT46R63/HT46C63
Labels C Bits 0 Function C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PDF is cleared by a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Status Register Bank Pointer The bank pointer is used to assign the accessed RAM bank. When the users want to access the RAM bank 0 a 0 should be loaded onto BP. When the BP is equal to 1, the LCD RAM will be accessed (use MP1/R1 indirect addressing only). RAM locations before 40H in any bank are overlapped. Accumulator The accumulator is closely related to ALU operations. It is also mapped to location 05H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ ....)
AC Z OV PDF TO 3/4
1 2 3 4 5 6, 7
tion operations related to the status register may give different results from those intended. The TO flag can be affected only by system power-up, a WDT time-out or executing the CLR WDT or HALT instruction. The PDF flag can be affected only by executing the HALT or CLR WDT instruction or a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. Interrupt The microcontroller provides two external interrupts, an internal timer/event counter overflow interrupt, a time b a se t i m e - o u t i n t e r r u p t , a n A / D co n ve r t e r end-of-conversion interrupt and a real time clock time-out interrupt. The interrupt control registers (INTC0: 0BH and INTC1: 1EH) contains the interrupt control bits to set the enable or disable and the interrupt request flags. Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may happen during this interval but only the interrupt request flags are recorded. If a certain interrupt requires servicing within the service routine, the programmer may set the EMI and the corresponding bit of INTC0/INTC1 to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decreased. If immediate service is desired, the stack has to be prevented from becoming full.
The ALU not only saves the results of a data operation but also changes the status register. Status Register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addi-
Rev. 1.90
11
May 17, 2004
HT46R63/HT46C63
All these kinds of interrupts have the wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack and then branching to subroutines at specified location(s) in the program memory. Only the program counter is pushed onto the stack. If the contents of the register or status register are altered by the interrupt service program, which corrupts the desired control sequence, the programmer should save these contents first. External interrupts are triggered by a high to low and/or low to high transition of INT0/INT1 and the related interrupt request flag (bit 4/5 of INTC0 ) will be set. When the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 004H/008H will occur. The external interrupt request flag and EMI bits will cleared to disable other interrupts. The internal timer/event counter interrupt is initialized by setting the timer/event counter interrupt request flag (bit 6 of INTC0), caused by a timer overflow. When the interrupt is enabled, the stack is not full and the timer/event counter interrupt request flag is set, a subroutine call to location 00CH will occur. The related interrupt request flag will be reset and the EMI bit cleared to disable further interrupts. The time base time-out interrupt is initialized by setting the time base time-out interrupt request flag (bit 4 of INTC1), caused by a time base time-out. When the interrupt is enabled, the stack is not full and the time base time-out interrupt request flag is set, a subroutine call to location 010H will occur. The related interrupt request flag will be reset and the EMI bit cleared to disable further interrupts. The A/D converter end-of-conversion interrupt is initialized by setting the A/D end-of-conversion interrupt request flag (bit 5 of INTC1), caused by an end of A/D conversion. When the interrupt is enabled, the stack is not full and the end of A/D conversion interrupt request flag is set, a subroutine call to location 014H will occur. The related interrupt request flag will be reset and the EMI bit cleared to disable further interrupts. The real time clock time-out interrupt is initialized by setting the real time clock interrupt request flag (bit 6 of INTC1), caused by a RTC time-out. When the interrupt is enabled, the stack is not full and the RTC time-out interrupt request flag is set, a subroutine call to location 018H will occur. The related interrupt request flag will be reset and the EMI bit cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (of course, if the stack is not full). To return from the interrupt subroutine, RET or RETI may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Rev. 1.90 12 Interrupts, occurring in the interval between rising edge of two consecutive T2 pulses, will be serviced on the later of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the priorities in the follow table apply. These can be masked by clearing the EMI bit. Interrupt Source External Interrupt 0 External Interrupt 1 Timer/Event Counter Overflow Interrupt Time Base Time-out Interrupt End of A/D Conversion Interrupt RTC Time-out Interrupt Priority 1 2 3 4 5 6 Vector 004H 008H 00CH 010H 014H 018H
The external interrupt 0/1 request flags (EI0F/EI1F), timer/event counter interrupt request flag (TF), time base interrupt request flag (TBF), A/D converter interrupt request flag (ADF), RTC interrupt request flag (RTF), enable external interrupt 0/1 (EE0I/EE1I), enable timer/event counter interrupt bit (ETI), enable time base interrupt (ETBI), enable A/D converter interrupt (EADI), enable RTC interrupt (ERTI) and enable master interrupt bit(EMI) constitute interrupt control registers (INTC0/INTC1) which is located at 0BH/1EH in the data memory. EMI, EE0I, EE1I, ETI, EADI and ERTI are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupts from being serviced. Once the interrupt request flags (EI0F, EI1F, TF, TBF, ADF, RTF) are set, they will remain in the INTC0/INTC1 until the interrupts are serviced or cleared by software instructions. It is suggested that a program does not use the call within a interrupt subroutine. It because interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged once the CALL operates in the interrupt subroutine. The definitions of INTC0 and INTC1 registers are as shown. Bit No. Label INTC0 Register 0 1 2 3 4 EMI EEI0 EEI1 ETI EIF0 Controls the master (global) interrupt (1= enabled; 0= disabled) Controls the external interrupt 0 (1= enabled; 0= disabled) Controls the external interrupt 1 (1= enabled; 0= disabled) Controls the timer/event counter overflow interrupt (1= enabled; 0= disabled) External interrupt 0 request flag (1= active; 0= inactive) Function
May 17, 2004
HT46R63/HT46C63
Bit No. Label 5 6 7 EIF1 TF 3/4 Function External interrupt 1 request flag (1= active; 0= inactive) Timer/Event Counter overflow request flag (1= active; 0= inactive) Unused bit, read as 0 are determined by options. The HALT mode stops the system oscillator and resists the external signal to conserve power. Another one is a 32768Hz crystal oscillator, which only provides use for real time clock. The other one is a built-in 12KHz RC oscillator, which is used for WDTOSC. If the system clock uses the external RC oscillator, an external resistor between OSC1 and VDD is required and the resistance should range from 24kW to 1MW. The system clock, divided by 4, is available on OSC2, which can be used to synchronize external logic. If the system clock uses the crystal oscillator, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are demanded. Instead of a crystal, the resonator can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required. If the RTCOSC is used, a crystal across OSC3 and OSC4 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are demanded. Watchdog Timer - WDT The clock source of WDT (and LCD, RTC, Time Base ) is implemented by a dedicated crystal oscillator (32.768kHz: RTCOSC) or instruction clock (system frequency divided by 4: fSYS/4) or a dedicated RC oscillator (12KHz:WDTOSC) decided by options. This timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable
OSC3 OSC1 OSC2 C r y s ta l O s c illa to r fo r s y s te m c lo c k fS Y S /4 N M O S O p e n D r a in OSC2 32768H z X 't a l OSC4 C r y s ta l O s c illa to r fo r R T C O S C
INTC1 Register 0 1 2 3 4 5 6 7 ETBI EADI ERTI 3/4 TBF ADF RTF 3/4 Controls the time base interrupt (1= enabled; 0= disabled) Controls the A/D converter interrupt (1= enabled; 0= disabled) Controls the real time clock interrupt (1= enabled; 0= disabled) Unused bit, read as 0 Time base time-out interrupt 0 request flag (1= active; 0= inactive) End of A/D conversion interrupt request flag (1= active; 0= inactive) RTC time-out interrupt request flag (1= active; 0= inactive) Unused bit, read as 0
Oscillator Configuration There are four oscillator circuits implemented in the micro-controller. Two of them are designed for system clocks, namely the external RC oscillator and the crystal oscillator, which
V OSC1
DD
E x te r n a l R C O s c illa to r fo r s y s te m c lo c k
System Oscillator
W DTOSC fS Y S /4 RTCOSC M U X CLRW DT fS 1 6 - B it C o u n te r RES 1 5 - B it C o u n te r D W D T tim e - o u t
O p tio n s O p tio n s R T C C .2 ~ R T C C .0
4 to 1 M U X 7 to 1 M U X 8 to 1 M U X
T im e b a s e : fS /2
12
~ fS /2
15
L C D fre q u e n c y : fS /2 2~ fS /2
8
RTC
: fS /2 8~ fS /2
15
Watchdog Timer
Rev. 1.90
13
May 17, 2004
HT46R63/HT46C63
results. The watchdog timer can be disabled by options. If the watchdog timer is disabled, all the executions related to the WDT result in no operation. The WDT time-out period is fixed as 216/fS. The fS means the clock frequency of WDT, time base, RTC and LCD. If WDTOSC is selected as the WDT clock, the time-out period may vary with temperatures, VDD and process variations. The WDTOSC and RTCOSC can be still running (decided by option) at the halt mode if they are selected as the WDT clock source. Once the 32.768kHz oscillator (with a period of 31.25ms normally) is selected to be the clock source of WDT (and LCD, RTC, Time Base), it is directly divided by 216 to get the nominal time-out period of 2 seconds. If the WDT clock comes from the instruction clock, the WDT will stop counting and lose its protecting purpose in halt mode. In this situation the logic can only be restarted by external logic. If the device operates in a noisy environment, using the RTCOSC or WDTOSC is strongly recommended, since the HALT will stop the system clock. The overflow of WDT under normal operation will initialize chip reset and set the status bit TO. But in the HALT mode, the overflow will initialize a warm reset, and only the PC and SP are reset to zero. To clear the contents of WDT , 3 methods are adopted; external reset (a low level to RES), software instruction(s) and a HALT instruction. The software instruction(s) include CLR WDT and the other set - CLR WDT1 and CLR WDT2 Of these two types of instruction, only one can be active depending on the options - CLR WDT times selection option. If the CLR WDT is selected (i.e. CLRWDT times equal one), any execution of the CLR WDT instruction will clear the WDT. In the case that CLR WDT1 and CLR WDT2 are chosen (i.e. CLR WDT times equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip as a result of time-out. The RTC oscillator should be designed as an auto-speed-up oscillator. After the RTC oscillator is oscillating, the auto-speed-up should be turned off. Time Base Generator There is a time base generator implemented in the micro-controller. The time base generator provides time-out periods selection whose range from fS/212 to fS/215. When the time base time-out occurs and the stack is not full and the time base interrupt is enabled, an interrupt subroutine call to ROM location 010H will activate. RTC Generator There is an RTC generator implemented in the micro-controller. The RTC generator provides software configurable real time clock periods whose range from fS/28 to fS/215. When the RTC time-out occurs and the stack is not full and the RTC interrupt is enabled, an inRev. 1.90 14 terrupt subroutine call to ROM location 018H will activate. The RTCC is the real time clock control register used to select the division ratio of RTC clock sources. RTCC.7~RTCC.3 cannot be used. RTCC.2 RTCC.1 RTCC.0 RTC clock divided factor 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 28 29 210 211 212 213 214 215
Power Down Operation - HALT The HALT mode is initialized by the HALT instruction and results in the following...
* The system oscillator will be turned off but the
WDTOSC or RTCOSC will stop or keep running decided by option (If the WDTOSC or RTCOSC is selected)
* The contents of the on-chip RAM and registers remain
unchanged.
* WDT will be cleared and recounted again (if the WDT
clock is from the WDTOSC or RTCOSC).
* All of the I/O ports maintain their original status. * The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a warm reset. After the TO and PDF flags are examined, the reason for chip reset can be determined. The PDF flag is cleared by system power-up or executing the CLR WDT instruction and is set when executing the HALT instruction. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the PC and SP; the others keep their original status. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by the option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it is awakening from an interrupt, two sequences may happen. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the HALT mode, the wake-up function of the related interrupt will be disabled.
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HT46R63/HT46C63
Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period will be inserted after wake-up. If the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. The 32.768kHz crystal oscillator still run or stop in the halt mode. (decided by option) Reset There are three ways in which a reset can occur:
* RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal operation
10kW 0 .1 m F * 100kW RES
The chip reset statuses of the functional units are as shown. PC Interrupt WDT 000H Disable Clear. After master reset, WDT begins counting
Timer/Event Counter Off Input/Output Ports SP Input mode Points to the top of the stack
V
DD
0 .0 1 m F *
The WDT time-out during HALT is different from other chip reset conditions, since it can perform a warm re set that resets only the PC and SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers are reset to the initial condition when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different chip resets. TO PDF 0 u 0 1 1 0 u 1 u 1 Reset Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT
Reset Circuit Note: * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference.
HALT W DT
RES
W a rm
R eset
OSC1
SST 1 0 - b it R ip p le C o u n te r S y s te m R eset
C o ld R eset
Note: u means unchanged To guarantee that the system oscillator is started and stabilized, the SST (system start-up timer) provides an extra-delay to delay 1024 system clock pulses when system power-up or the system awakes from the HALT state. When the system power-up occurs, the SST delay is added during the reset period. But when the reset comes from the RES pin, the SST delay is disabled. Any wake-up from HALT will enable the SST delay. An extra option load time delay is added during system reset (power-up, WDT time-out at normal mode or RES reset).
Reset Configuration
VDD RES S S T T im e - o u t C h ip R eset tS
ST
Reset Timing Chart
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May 17, 2004
HT46R63/HT46C63
The registers states are summarized in the following table. Register MP0 MP1 BP ACC PCH.PCL TBLP TBLH RTCC STATUS INTC0 INTC1 TMRL TMRH TMRC PA PAC PB PBC PC PCC PD PDC PWM0 PWM1 PWM2 PWM3 ADR ADCR ACSR Note: Reset (Power On) xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx 000H xxxx xxxx -xxx xxxx --xx x111 --00 xxxx -000 0000 -000 -000 xxxx xxxx xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0100 0000 0--- -100 * stands for warm reset u stands for unchanged x stands for unknown WDT Time-out RES Reset (Normal Operation) (Normal Operation) uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 000H uuuu uuuu -uuu uuuu --xx x111 --1u uuuu -000 0000 -000 -000 xxxx xxxx xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0100 0000 0--- -100 uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 000H uuuu uuuu -uuu uuuu --xx x111 --uu uuuu -000 0000 -000 -000 xxxx xxxx xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0100 0000 0--- -100 RES Rese (HALT) uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 000H uuuu uuuu -uuu uuuu --xx x111 --01 uuuu -000 0000 -000 -000 xxxx xxxx xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0100 0000 0--- -100 WDT Time-out (HALT)* uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 000H uuuu uuuu -uuu uuuu --uu uuuu --11 uuuu -uuu uuuu -uuu -uuu uuuu uuuu uuuu uuuu uu-u u--uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u--- -uuu
Rev. 1.90
16
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Timer/Event Counter A timer/event counter is implemented in the device. The timer/event counter contains a 16-bit programmable count-up counter and the clock may come from an external source or the internal clock source. The internal clock source is the system clock divided by 4: fSYS/4. The external clock input allows the user to count external events, measure time intervals or pulse widths, or to generate an accurate time base. There are 3 registers related to timer/event counter; TMRH(0CH), TMRL(0DH), TMRC(0EH). Writing TMRL only stores the data into a low byte buffer, and writing TMRH will put the written data and the low contents of low byte buffer to preload register (16 bits) simultaneously. The timer/event counter preload register is changed by writing TMRH operations and writing TMRL will keep the timer/event counter preload register unchanged. Reading TMRH will also latch the TMRL into the low byte buffer to avoid the false timing problem. Reading TMRL returns the contents of the low byte buffer. In other words, the low byte of timer/event counter cannot be read directly. It has to read the TMRH first to make the low byte contents of timer/event counter latched into the buffer. The TMRC is the timer/event counter control register, which defines the operating mode, counting enable or disable and active edge. The TM0, TM1 bits define the operating mode. The event count mode is used to count external events, which means the clock source comes from an external (TMR) pin. The timer mode functions as a normal timer with the clock source coming from fSYS/4. The pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR). The counting is based on fSYS/4. In the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to FFFFH. Once
fS
YS
overflow occurs, the counter is reloaded from the timer/event counter preload register and generates the corresponding interrupt request flag (TF; bit 6 of INTC0) at the same time. In pulse width measurement mode with the TON and TE bits are equal to one, once the TMR has received a transition from low to high (or high to low if the TE bit is 0) it will start counting until the TMR returns to the original level and reset the TON. The measured result will remain in the timer/event counter even if the activated transition occurs again. In other words, only one cycle measurement can be done. Until setting the TON, the cycle measurement will function again as long as it receives further transition pulse. Note that, in this operating mode, the timer/event counter starts counting not according to the logic level but according to the transition edges. In the case of counter overflows, the counter is reloaded from the timer/event counter preload register and issues the interrupt request just like the other two modes. To enable the counting operation, the timer ON bit (TON; bit 4 of TMRC) should be set to 1. In the pulse width measurement mode, the TON will be cleared automatically after the measurement cycle is complete. But in the other two modes the TON can only be reset by instructions. The overflow of the timer/event counter is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ETI can disabled the corresponding interrupt service. In the case of timer/event counter OFF condition, writing data to the timer/event counter preload register will also load the data to timer/event counter. But if the timer/event counter is turned on, data written to the timer/event counter will only be kept in the timer/event counter preload register. The timer/event counter will still operate until the overflow occurs (a timer/event counter reloading will occur at the same time).
/4
TM R TE TM 1 TM 0 TON
TM 1 TM 0
D a ta B u s 1 6 - B it T im e r /e v e n t C o u n te r P r e lo a d R e g is te r 1 6 - B it T im e r /e v e n t C o u n te r (T M R H , T M R L ) 8 - B it L o w B y te B u ffe r R e lo a d
P u ls e W id th M e a s u re m e n t M o d e C o n tro l
O v e r flo w
to In te rru p t
Timer/Event Counter
Rev. 1.90
17
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HT46R63/HT46C63
When the timer/event counter (reading TMRH) is read, the clock will be blocked to avoid errors. As this may results in a counting error, this must be taken into consideration by the programmer. Label Bits (TMRC) 3/4 Function 16H or 18H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC, PCC, PDC) to control the input/output configuration. With this control register, CMOS output or schmitt trigger input with or without (depends on options) pull-high resistor structures can be reconfigured dynamically (i.e., on-the fly) under software control. To function as an input, the corresponding latch of the control register has to be set as 1. The pull-high resistor (if the pull-high resistor is enabled) will be exhibited automatically. The input sources are also dependent on the control register. If the control register bit is 1, the input will read the pad state (mov and read-modify-write instructions). If the control register bit is 0, the contents of the latches will move to internal data bus (mov and read-modify-write instructions). The input paths (pad state or latches) of read-modify-write instructions are dependent on the control register bits. For output function, CMOS is the only configuration. These control registers are mapped to locations 13H, 15H, 17H and 19H. After a chip reset, these input/output lines stay at a high level (pull-high options) or floating state (non-pull-high options). Each bit of these input/output latches can be set or cleared by SET [m].i (m=12H, 14H, 16H or 18H) instructions. Some instructions first input data and then follow the output operations. For example, SET [m].i CLR [m].i, CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation),
V C o n tr o l B it D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r D CK Q S PA0 PB0 PC0 PD0 ~PA ~PB ~PC ~PD 7 7 7 7 Q PH
DD
0~2 Unused bits, read as 0 To define the active edge of TMR pin input signal (0=active on low to high; 1=active on high to low) To enable or disable timer counting (0=disabled; 1=enabled) Unused bit, read as 0 To define the operating mode 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMRC Register
TE
3
TON 3/4
4 5
TM0 TM1
6 7
Input/Output Ports There are 32 bi-directional input/output lines in the micro-controller, labeled from PA to PD, which are mapped to the data memory of [12H], [14H], [16H] and [18H], respectively. All of these I/O ports can be used as input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H,
D a ta B it Q D CK S Q
W r ite D a ta R e g is te r PW M 0~PW M 3 ( P D 0 ~ P D 3 O n ly )
M U R e a d D a ta R e g is te r S y s te m W a k e -u p ( P A o n ly )
X W a k e - u p o p tio n s
T o In te rru p t
P u ls e G e n e r a to r D is a b le /H ig h /L o w H ig h - L o w E d g e to P u ls e PD 4 and PD5
Input/Output Ports Rev. 1.90 18 May 17, 2004
HT46R63/HT46C63
and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. The pull-high resistor of each I/O line is decided by options. Comparator T h e re i s a c om par a t o r i m pl e m e n t e d i n t h i s microcontroller. This comparator can be enabled/disabled by options. Its inputs are CMPP(+) and CMPN(-) and outputs are CMPO and CHGO. When the CMPN input level is less than the level of CMPP, the CMPO output is VDD. When the CMPN input level is higher than the level of CMPP, the CMPO output is VSS. The CHGO signal is combined with CMPO and 32768Hz carrier if 32768Hz RTC oscillator is applied. This comparator also can be disabled by options. When the system enters halt mode, the comparator is disabled to reduce power consumption. Once the comparator is disabled, the CHGO and CMPO will stay at VSS level. LCD Display Memory The micro-controller provides an area of embedded data memory for LCD driver. This area is located from 40H to 53H of he RAM Bank 1. Bank pointer (BP; located at 04H of the RAM) is the switch between the general purpose RAM and the LCD display memory. When the BP is set to 1, any data written into 40H~53H (indirect accessing by using the MP1and R1) will effect the LCD display. When the BP is cleared to 0, any data
COM 0 1 2 3 3 2 1 Addr 40H 41H 42H 43H
written into 40H to 53H will access the general purpose data memory. The LCD display memory can be read and written to only by indirect addressing mode using MP1. When data is written into the display data area it is automatically read by the LCD driver which then generates the corresponding LCD driving signals. To turn the display on or off, an 1 or a 0 is written to the corresponding bit of the display memory, respectively. The figure illustrates the mapping between the display memory and LCD pattern for the micro-controller. LCD Driver Output and Bias Circuit The output number of the micro-controller LCD driver can be 203 or 194 by options (ie., 1/3 duty or 1/4 duty). The bias type of LCD driver is R type, no external capacitor is required. The LCD can be optioned as LCD on at HALT or LCD off at HALT which are dependent on options. The SEG7~SEG18 also can be optioned as logical outputs. Each group of SEG7~SEG10, SEG11~SEG14 and SEG15~SEG18 can be optioned individually. Once an LCD segment is optioned as a logical output, the contents of bit 0 of the related segment address in LCD RAM will appear on the segment. Memory Bit 0=0 Bit 0=1 Segment Output VSS VDD
Logical Output Function
4FH
50H
51H
52H
53H 0
B it
SEGMENT
0
1
2
3
15
16
17
18
19
Display Memory
Rev. 1.90
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HT46R63/HT46C63
D u r in g a r e s e t p u ls e CO M 0,CO M 1,CO M 2 V3 V2 V1 V0 V3 A ll L C D d r iv e r o u tp u ts N o r m a l o p e r a tio n m o d e COM0 COM1 V3 V2 V1 V0 V3 V2 V1 V0 COM2 V3 V2 V1 V0 V3 COM3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V2 V1 V0
L C D s e g m e n ts o n C O M 0 , 1 , 2 , 3 s id e s a r e u n lig h te d O n ly L C D s e g m e n ts o n C O M 0 s id e s a r e lig h te d O n ly L C D s e g m e n ts o n C O M 2 s id e s a r e lig h te d L C D s e g m e n ts o n C O M 0 , 1 s id e s a r e lig h te d L C D s e g m e n ts o n C O M 0 , 2 s id e s a r e lig h te d L C D s e g m e n ts o n C O M 0 , 1 , 2 s id e s a r e lig h te d
H A L T m o d e (L C D o ff a t H A L T ) CO M 0,CO M 1,CO M 2 V3 V2 V1 V0 V3 V2 V1 V0
A ll L C D d r iv e r o u tp u ts
LCD Driver Outputs (1/4 Duty, 1/3 Bias) Note: If LCD is turned on at HALT mode, the LCD outputs are dependent on LCD display memory. If LCD is turned off at HALT mode, the power will be V3=V2=V1=V0=VDD
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HT46R63/HT46C63
V
DD
E x te rn a l R VLCD V3 V2 V1 N o te : B ia s c u r r e n t ( lo w , m id d le o r h ig h ) is s e le c ta b le b y R O M c o d e o p tio n . L C D O ff: V 0 = V 1 = V 2 = V 3 = V L C D ( = V D D , if c o n n e c t V L C D to V D D w ith e x te r n a l r e s is to r ) L C D d r iv e r a n d b ia s O n : V 0 = V S S ,V 1 = V L C D /3 ,V 2 = V L C D * 2 /3 ,V 3 = V L C D *V
DD
V0 L C D O n /O ff ** V
= Low M id H ig
5 V , B ia :8mA, d le : 1 6 h:48mA ,B mA :1 8m
s fo e x te mA, ,ex
r V LC D = rn a l R = e x te rn a te rn a l R V
3V 240kW lR =120kW =40kW
DD=3V Low :8 M id d le H ig h : 4
ia s fo r , e x te rn 6mA,ex A , e x te
LC D = 3 V alR =0kW te rn a l R = 0 k W rn a l R = 0 k W
LCD Bias Block Diagram and Application Circuit
A/D Converter The 8 channels and 8-bit resolution (7-bit accuracy) A/D converter are implemented in this microcontroller. The reference voltage is AVDD. The AVDD pin must be connected to VDD externally. Conversion accuracy may therefore be degraded by voltage drops and noise in the event of heavily loaded or badly coupled power supply lines. The A/D converter contains 3 special registers which are; ADR (21H), ADCR (22H) and ACSR (23H). The ADR is A/D result register. After the A/D conversion is completed, the ADR should be read to get the conversion result data. The ADCR is an A/D converter control register, which defines the A/D channel number, analog channel select, start A/D conversion control bit and the end of A/D conversion flag. If the users want to start an A/D conversion, after select the converted analog channel, and then give START bit a positive pulse (0(R)1(R)0). At the end of A/D conversion, the EOCB bit is cleared and an A/D converter interrupt occurs(if the A/D converter interrupt is enabled). The ACSR is an A/D clock setting register, which is used to select the A/D clock source. The A/D converter control register is used to control the A/D converter. The bit2~bit0 of the ADCR are used to select an analog input channel. There are a total of 8
channels to select. The bit5~bit3 of the ADCR are used to set PB configurations. PB can be an analog input or as digital I/O line decided by these 3 bits. Once a PB line is selected as an analog input, the I/O functions and pull-high resistor of this I/O line are disabled. The EOCB bit (bit 6 of the ADCR) is end of A/D conversion flag. Check this bit to know when A/D conversion is completed. The START bit of the ADCR is used to begin the conversion of A/D converter. Give START bit a falling edge that means the A/D conversion has started. The A/D converter remains in reset state while the START stays at 1. In order to ensure the A/D conversion is completed, the START should stay at 0 until the EOCB is cleared to 0 (end of A/D conversion). The bit 7 of the ACSR is used for testing purpose only. It can not be used for the users. The bit1 and bit0 of the ACSR are used to select A/D clock sources. When the A/D conversion is completed, the A/D interrupt request flag is set. The bit is set to 1 when the START bit is set to 1. Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADR D7 D6 D5 D4 D3 D2 D1 D0
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Label (ADCR) Bits Functions ACS2, ACS1, ACS0: A/D channel selection 0,0,0: AN0 0,0,1: AN1 0,1,0: AN2 0,1,1: AN3 1,0,0: AN4 1,0,1: AN5 1,1,0: AN6 1,1,1: AN7 PCR2, PCR1, PCR0: PB7~PB0 pad functions 0,0,0: PB7, PB6, PB5, PB4, PB3, PB2, PB1, PB0 0,0,1: PB7, PB6, PB5, PB4, PB3, PB2, PB1, AN0 0,1,0: PB7, PB6, PB5, PB4, PB3, PB2, AN1, AN0 0,1,1: PB7, PB6, PB5, PB4, PB3, AN2, AN1, AN0 1,0,0: PB7, PB6, PB5, PB4, AN3, AN2, AN1, AN0 1,0,1: PB7, PB6, PB5, AN4, AN3, AN2, AN1, AN0 1,1,0: PB7, PB6, AN5, AN4, AN3, AN2, AN1, AN0 1,1,1: AN7, AN6, AN5, AN4, AN3, AN2, AN1, AN0 End of A/D conversion flag (0: end of A/D conversion) A/D conversion sequence (START=010) 0: Initial value after chip RESET 0(R)1: Initial next A/D conversion. 1: reset A/D converter and set EOCB to 1 1(R)0: Starts the A/D conversion. 0: Normal state for A/D
ACS0 ACS1 ACS2
0 1 2
PCR0 PCR1 PCR2
3 4 5
EOCB
6
START
7
Note:
It is recommended that START is 0 and PCR2~PCR0 is 000 before MCU entering HALT mode. HALT will not standby the A/D converter automatically. ACSR Register
Label (ACSR)
Bits
Functions ADCS1, ADCS0: Selects the A/D converter clock source 0,0: fSYS/2 0,1: fSYS/8 1,0: fSYS/32 1,1: Cannot be used Comparator control (*) 0: Disable 1: Enable Unused bit, read as 0 For test mode used only 0: Normal mode 1: TEST only, cannot be used
ADCS0 ADCS1
0 1
CMPC 3/4 TEST
2 3~6 7
Note:
* This bit is 0 during reset.
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The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example: using EOCB Polling Method to detect end of conversion clr INTC0.3 ; disable A/D interrupt in interrupt control register mov a,00100000B mov ADCR,a ; setup ADCR register to configure Port PB0~PB3 as A/D inputs and select ; AN0 to be connected to the A/D converter mov a,00000001B mov ACSR,a ; setup the ACSR register to select fSYS/8 as the A/D clock Start_conversion: clr ADCR.7 set ADCR.7 clr ADCR.7 Polling_EOC: sz ADCR.6 jmp polling_EOC mov a,ADR mov adr_buffer,a : : jmp start_conversion
; reset A/D ; start A/D
; poll the ADCR register EOCB bit to detect end of A/D conversion ; continue polling ; read conversion result from the high byte ADR register ; save result to user defined register
; start next A/D conversion
Example: using Interrupt method to detect end of conversion set INTC0.0 ; interrupt global enable set INTC0.3 ; enable A/D interrupt in interrupt control register mov a,00100000B mov ADCR,a ; setup ADCR register to configure Port PB0~PB3 as A/D inputs and select ; AN0 to be connected to the A/D converter mov a,00000001B mov ACSR,a ; setup the ACSR register to select fSYS/8 as the A/D clock start_conversion: clr ADCR.7 set ADCR.7 clr ADCR.7 : : ; interrupt service routine EOC_service routine: mov a_buffer,a mov a,ADR mov adr_buffer,a clr ADCR.7 set ADCR.7 clr ADCR.7 mov a,a_buffer reti
; reset A/D ; start A/D
; save ACC to user defined register ; read conversion result from the high byte ADR register ; save result to user defined register
; reset A/D ; start A/D ; restore ACC from temporary storage
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M in im u m o n e in s tr u c tio n c y c le n e e d e d
START EOCB A /D s a m p lin g tim e 3 2 tA D PC R2~PC R0 000B 100B A /D s a m p lin g tim e 3 2 tA D 100B 000B 1 . P B p o rt s e tu p a s I/O s 2 . A /D c o n v e r te r is p o w e r e d o ff to r e d u c e p o w e r c o n s u m p tio n AC S2~ACS0 000B P o w e r-o n R eset R e s e t A /D c o n v e rte r 1 : D e fin e P B c o n fig u r a tio n 2 : S e le c t a n a lo g c h a n n e l A /D N o te : A /D c lo c k m u s t b e fS
YS
010B S ta rt o f A /D c o n v e r s io n
000B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n
d o n 't c a r e
E n d o f A /D c o n v e r s io n 6 4 tA D c o n v e r s io n tim e
6 4 tA D c o n v e r s io n tim e
YS
A /D
/2 , fS
/8 o r fS
YS
/3 2
A/D Conversion Timing PWM The micro-controller provides 4 channels (6+2) bits PWM outputs shared with PD0~PD3. The PWM channels has their data register. The PWMs uses a PWM counter whose stages are 8 (stage 1~stage 8: fSYS/21 ~ fSYS/28). The frequency source of the PWM counter comes from fSYS. The PWM register is an eight bits register. The waveforms of PWM outputs are as shown. Once the PDi (i=0~3) is selected as the PWMi output and the output function of PDi is enabled, writing 1 to PDi data register will enable the PWMi output function. Otherwise the PDi will stay at 0. The PWM modulation frequency, PWM cycle frequency and PWM cycle duty are summarized in the following table. PWMi Modulation Frequency fSYS/64 PWMi Cycle Frequency fSYS/256 PWMi Cycle Duty [PWM]/256
fS
YS
/2
[P W M ] = 1 0 0 PW M [P W M ] = 1 0 1 PW M [P W M ] = 1 0 2 PW M [P W M ] = 1 0 3 PW M PW M 2 6 /6 4 m o d u la tio n p e r io d : 6 4 /fS M o d u la tio n c y c le 0
YS
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4 M o d u la tio n c y c le 1 PW M
2 6 /6 4 M o d u la tio n c y c le 2 c y c le : 2 5 6 /fS
YS
2 5 /6 4 M o d u la tio n c y c le 3
2 6 /6 4 M o d u la tio n c y c le 0
PWM Mode
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Options The following table shows all kinds of options in the microcontroller. All of the options must be defined to ensure proper system function. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 PA wake-up enable or disable (1/0) options WDT/LCD/RTC/Time Base Clock Source (fS): RTCOSC(32768Hz crystal), T1D or WDTOSC (*1) CLR WDT instructions: 1/2 WDT enable or disable PA pull-high enable or disable (1 option : 4 bits (0~3/4~7)) PB pull-high enable or disable (1 option : 4 bits (0~3/4~7)) PC pull-high enable or disable (1 option : 4 bits (0~3/4~7)) PD pull-high enable or disable (1 option : 4 bits (0~3/4~7)) INT0 or INT1 trigger edge: disable; high to low; low to high; low to high or high to low. COM3 or SEG19 (1/4 or 1/3 duty) LCD on/off at halt mode enable or disable Comparator enable or disable PWMi function for PDi (bit optional) fS/212~fS/215: Time base period SEG7~SEG18 logical or LCD output (1 option: 4 bits (SEG7~SEG10/SEG11~SEG14/SEG15~SEG18)) System oscillators: external RC/ external crystal enable or disable RTCOSC(32.768kHz crystal) or WDTOSC at HALT mode LCD bias current: Low/Middle/High driving current LCD driver clock selection. There are seven types of frequency signals for the LCD driver circuits: fS/22~fS/28, fS stands for the clock source selection by options. *1 T1D is stopped at HALT; RTCOSC(32.768kHz crystal) and WDT OSC are stopped or non-stopped at HALT decided by option(18). Options
Note:
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Application Circuits
V
DD
0 .0 1 m F * 100kW 0 .1 m F
10kW
VDD RES
CO M 0~CO M 3 SEG 0~SEG 18 V VLCD
LCD PANEL
DD
0 .1 m F * VSS
AVDD PA0~PA7
V
DD
OSC C ir c u it S e e r ig h t s id e
OSC1 OSC2
P B 0 /A N 0 P B 7 /A N 7 V PC 0~PC 7 P D 0 /P W M 0 P D 3 /P W M 3 P D 4 /IN P D 5 /IN P D 6 /T P CMP CMP CMP CHG P O O ~ T0 T1 MR D7 N ~
DD
R
OSC
R C S y s te m O s c illa to r 24kW YS
470pF
/4
OSC2 OSC1 C ry s ta l S y s te m F o r th e v a lu e s , s e e ta b le b e lo w O s c illa to r
32768H z 10pF
OSC3
C1
OSC4
C2 R1
OSC2 O S C C ir c u it
H T 4 6 R 6 3 /H T 4 6 C 6 3
The following table shows the C1, C2 and R1 value according different crystal values. Crystal or Resonator 4MHz Crystal 4MHz Resonator (3 pin) 4MHz Resonator (2 pin) 3.58MHz Crystal 3.58MHz Resonator (2 pin) 2MHz Crystal & Resonator (2 pin) 1MHz Crystal 480kHz Resonator 455kHz Resonator 429kHz Resonator Note: C1, C2 0pF 0pF 10pF 0pF 25pF 25pF 35pF 300pF 300pF 300pF R1 10kW 12kW 12kW 10kW 10kW 10kW 27kW 9.1kW 10kW 10kW
The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference.
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Instruction Set Summary
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected
Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z
Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z
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Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Description Instruction Cycle Flag Affected
x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged.
(2)
(3) (1) (4)
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Instruction Definition
ADC A,[m] Description Operation Affected flag(s) TO 3/4 ADCM A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,x Description Operation Affected flag(s) TO 3/4 ADDM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C
Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C
Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m]
Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x
Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m]
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AND A,[m] Description Operation Affected flag(s) TO 3/4 AND A,x Description Operation Affected flag(s) TO 3/4 ANDM A,[m] Description Operation Affected flag(s) TO 3/4 CALL addr Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m]
Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x
Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m]
Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack PC+1 PC addr TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CLR [m] Description Operation Affected flag(s)
Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
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CLR [m].i Description Operation Affected flag(s) TO 3/4 CLR WDT Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0
Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared. WDT 00H PDF and TO 0 TO 0 PDF 0 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
CLR WDT1 Description
Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* TO 0* PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CLR WDT2 Description
Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* TO 0* PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CPL [m] Description Operation Affected flag(s)
Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m] TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
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CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m] TO 3/4 DAA [m] Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
DEC [m] Description Operation Affected flag(s)
Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1 TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
DECA [m] Description Operation Affected flag(s)
Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1 TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
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HALT Description Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared. PC PC+1 PDF 1 TO 0 TO 0 INC [m] Description Operation Affected flag(s) TO 3/4 INCA [m] Description Operation Affected flag(s) TO 3/4 JMP addr Description Operation Affected flag(s) TO 3/4 MOV A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. PC addr PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 1 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1
Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1
Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m]
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MOV A,x Description Operation Affected flag(s) TO 3/4 MOV [m],A Description Operation Affected flag(s) TO 3/4 NOP Description Operation Affected flag(s) TO 3/4 OR A,[m] Description Operation Affected flag(s) TO 3/4 OR A,x Description Operation Affected flag(s) TO 3/4 ORM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 No operation No operation is performed. Execution continues with the next instruction. PC PC+1 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x
Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC
Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m]
Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x
Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m]
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RET Description Operation Affected flag(s) TO 3/4 RET A,x Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. PC Stack
Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. PC Stack ACC x TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RETI Description Operation
Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. PC Stack EMI 1 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RL [m] Description Operation
Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RLA [m] Description Operation
Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
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RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7 TO 3/4 RLCA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Affected flag(s)
Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
RR [m] Description Operation
Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RRA [m] Description Operation
Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RRC [m] Description Operation
Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Affected flag(s)
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RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0 TO 3/4 SBC A,[m] Description Operation Affected flag(s) TO 3/4 SBCM A,[m] Description Operation Affected flag(s) TO 3/4 SDZ [m] Description PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C
Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SDZA [m] Description
Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
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SET [m] Description Operation Affected flag(s) TO 3/4 SET [m]. i Description Operation Affected flag(s) TO 3/4 SIZ [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH
Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1
Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SIZA [m] Description
Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SNZ [m].i Description
Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
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SUB A,[m] Description Operation Affected flag(s) TO 3/4 SUBM A,[m] Description Operation Affected flag(s) TO 3/4 SUB A,x Description Operation Affected flag(s) TO 3/4 SWAP [m] Description Operation Affected flag(s) TO 3/4 SWAPA [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1
Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1
Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
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SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZ [m].i Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0
Operation Affected flag(s)
TO 3/4 TABRDC [m] Description Operation
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
TABRDL [m] Description Operation
Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
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XOR A,[m] Description Operation Affected flag(s) TO 3/4 XORM A,[m] Description Operation Affected flag(s) TO 3/4 XOR A,x Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m]
Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m]
Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x
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Package Information
56-pin SSOP (300mil) Outline Dimensions
56 A 1 C C'
29 B 28
G H a F
D E
Symbol A B C C D E F G H a
Dimensions in mil Min. 395 291 8 720 89 3/4 4 25 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 25 3/4 3/4 3/4 3/4 Max. 420 299 12 730 99 3/4 10 35 12 8
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100-pin QFP (1420) Outline Dimensions
C D 80 51 G H
I 81 50
F A B
E
100
31 K 1 30 a J
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 18.50 13.90 24.50 19.90 3/4 3/4 2.50 3/4 3/4 1 0.10 0 Nom. 3/4 3/4 3/4 3/4 0.65 0.30 3/4 3/4 0.10 3/4 3/4 3/4 Max. 19.20 14.10 25.20 20.10 3/4 3/4 3.10 3.40 3/4 1.40 0.20 7
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Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031 Tel: 0755-8346-5589 Fax: 0755-8346-5590 ISDN: 0755-8346-5591 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holmate Semiconductor, Inc. (North America Sales Office) 46712 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright O 2004 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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